1. Field of the Invention
The present invention relates to a plasma display panel (PDP) driver and a driving method thereof.
2. Discussion of the Related Art
Recently, liquid crystal displays (LCDs), field emission displays (FEDs), and plasma displays have been actively developed. Plasma displays have better luminance and light emission efficiency as compared to other types of flat panel devices, and they also have wider view angles. Therefore, the plasma displays have come into the spotlight as substitutes for the conventional cathode ray tubes (CRTs) in large displays of greater than 40 inches.
The plasma display is a flat display that uses plasma generated by a gas discharge process to display characters or images, and tens to millions of pixels are provided thereon in a matrix format, depending on its size. Plasma displays are categorized into DC plasma displays and AC plasma displays, according to supplied driving voltage waveforms and discharge cell structures.
Since the DC plasma displays have electrodes exposed in the discharge space, they allow a current to flow in the discharge space while the voltage is supplied, and therefore they problematically require resistors for current restriction. On the other hand, since the AC plasma displays have electrodes covered by a dielectric layer, capacitances are naturally formed to restrict the current, and the electrodes are protected from ion shocks in the case of discharging. Accordingly, they have a longer lifespan than the DC plasma displays.
FIG. 1 shows a perspective view of an AC PDP. As shown, a scan electrode 4 and a sustain electrode 5, disposed over a dielectric layer 2 and a protection film 3, are provided in parallel and form a pair with each other under a first glass substrate 1. A plurality of address electrodes 8 covered with an insulation layer 7 are installed on a second glass substrate 6. Barrier ribs 9 are formed in parallel with the address electrodes 8, on the insulation layer 7 between the address electrodes 8, and phosphor 10 is formed on the surface of the insulation layer 7 between the barrier ribs 9. The first and second glass substrates 1, 6 having a discharge space 11 between them are provided facing each other so that the scan electrode 4 and the sustain electrode 5 may respectively cross the address electrode 8. The address electrode 8 and a discharge space 11 formed at a crossing point of the scan electrode 4 and the sustain electrode 5 form a discharge cell 12.
FIG. 2 shows a typical PDP electrode arrangement diagram. As shown, the PDP electrode has an m×n matrix configuration. It has address electrodes A1 to Am in a column direction, and scan electrodes Y1 to Yn and sustain electrodes X1 to Xn in a row direction, alternately. The scan electrodes will be referred to as Y electrodes and the sustain electrodes as X electrodes hereinafter. The discharge cell 12 shown in FIG. 2 corresponds to the discharge cell 12 shown in FIG. 1.
Typically, the AC PDP driving method includes a reset period, an addressing period, and a sustain period according to temporally varied operations. In the reset period wall charges caused by a previous sustain discharge are erased and the cells are reset in order to stably perform a next address operation. In the address period, the cells that are turned on and the cells that are not turned on are selected on the panel, and wall charges are accumulated on the cells that are turned on (i.e., the addressed cells). In the sustain period, a discharge for actually displaying pictures on the addressed cells is performed by alternately applying a sustain discharge pulse of Vs to the scan and sustain electrodes.
FIG. 3 shows a conventional PDP Y electrode driver 320 circuit diagram. As shown, the Y electrode driver 320 includes a reset driver 321, a scan driver 322, and a sustain driver 323.
The reset driver 321 includes a rising ramp switch Yrr for generating a rising reset waveform, a falling ramp switch Yrr for generating a falling ramp waveform in a reset period, a power source Vset, a capacitor Cset operable as a floating power source, and a switch Ypp.
The scan driver 322 generates a scan pulse in the address period, and includes a power source VscH for supplying a voltage to a scan electrode which is not selected, a capacitor Csc for storing the voltage VscH, and a plurality of scan driver ICs coupled to the Y electrodes. The scan driver IC includes a switch YscH for supplying the high voltage VscH to the panel capacitor Cp, and a switch YscL for supplying a low voltage 0V.
The sustain driver 323 generates a sustain discharge pulse in the sustain period, and includes switches Ys, Yg coupled between the power source Vs and the ground GND.
In the prior art, when a reset waveform is applied to the Y electrode in the reset period, the switch Ypp is turned off to prevent applying a voltage which is higher than the sustain discharge voltage Vs applied to the sustain driver 323, and the current path coupled to the Y electrode from the capacitor Cset allows a voltage to be applied which is higher than the voltage Vs to the Y electrode through the capacitor Cset and the switch Yrr.
The maximum voltage of a circuit is determined by the maximum voltage applied in the reset period, typically ranging from 300 to 500V. Therefore, when the above-noted large withstanding voltage is applied to the sustain driver 323, the withstanding voltages of elements of the sustain driver 323 are increased, and hence, a switch Ypp is needed between the capacitor Cset and the switch Yrr, as shown FIG. 3, in order to prevent the increase of the withstanding voltages.
However, since the switch Ypp must withstand the large amount of current at the time of a sustain discharge and the high voltages which are applied in the reset period, it is required to use expensive elements with high withstanding voltages. Also, since the switch Ypp is coupled to a main path from which the sustain discharge waveform is output, voltages may be dropped or waveforms may be distorted when the currents flow.